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1. Field of the Invention
The present invention relates to radar receivers. More specifically, the present invention relates to equalization systems used in high performance digital radar receivers.
2. Description of the Related Art
Sophisticated high performance military and commercial digital radar receivers detect and process signals in complicated environments that include broadband clutter, interference sources (intentional and unintentional), echoes, and receiver noise. These receivers perform some or all of the following functions: synthesis of in-phase (I) and quadrature (Q) components from high-speed sampled signals, formation of video filters, notch DC components, decimation of data, provision of channel-to-channel equalization, digital range correlation, beam steering and interference cancellation.
Currently, these tasks are performed by Hilbert filters, digital video filters, equalization filters, discrete Fourier transform filters, decimating filters, convolvers, correlators, and general purpose cascadable finite impulse response (FIR) filters implemented in commercial off-the-shelf hardware (COTS) and customized hardware in embedded systems.
Unfortunately, digital radar receivers implemented in accordance with conventional teachings often require several hundred signal processing chips. As a result, conventional digital radar receivers are typically heavy, bulky, and expensive to develop and manufacture. In addition, these receivers typically consume considerable power and generate much heat.
Hence, there was a need in the art for a unique receiver architecture that would be highly flexible, scalable, and reconfigurable that could perform the numerous functions mentioned above. The need in the art was addressed by copending application entitled GENERAL PURPOSE FILTER, filed Ser. No. 09/593,203, by L. C. Cox et al. (Atty. Docket No. PD R98027-1), the teachings of which are incorporated by reference. This application disclosed and claimed a signal processor design including a plurality of filters which were selectively interconnected to provide a variety of digital signal processing functions. In the illustrative embodiment, each filter was adapted to multiply input data by a coefficient. Specifically, each filter was adapted to multiply input data by coefficients to form digital filtering products which were combined to accumulate the sum of the products. The coefficients are provided by a microprocessor and configure the logic to a particular function, such as a general purpose filter, a Hilbert filter, a finite impulse response filter, an equalizer, a convolver, a correlator, or an application specific integrated circuit by way of example. When interconnected in accordance with the teachings provided therein, these circuits may be used to provide a digital receiver.
The digital receiver would comprise a plurality of general purpose filters constructed in accordance with the referenced teachings. Each filter would have a plurality of filter banks, switching circuitry to interconnect the filter banks, and programmability provided by an external processor. The processor would configure the filter banks, to provide a delay element, a first decimating filter and a first equalizer in a first channel of a first general purpose filter and a Hilbert transform, a second decimating filter and a second equalizer in a second channel of the first general purpose filter. A first range correlator would be provided in a first channel of a second general purpose filter and a second range correlator would be provided in a second channel of a second general purpose filter. The first channel of the first general purpose filter would be connected to the first channel of the second general purpose filter and the second channel of the first general purpose filter would be connected to the second channel of the second general purpose filter.
An external processor would program the general purpose filter to configure the filter banks to simultaneously provide the functions found in most digital receivers (e.g., Hilbert transforms, video filters, equalizers, range correlation, and general purpose video filters).
The versatile, flexible and reusable features of the general purpose filter architecture allows analog and digital receivers to be built using a single chip type. Accordingly, the receivers would be much smaller and lighter in weight than conventional systems and have lower associated power dissipation, thermal heating, and development and manufacturing cost.
While the teachings of the referenced patent application substantially addressed the need in the art, a need remains for a system and technique for implementing equalization in a digital radar receiver using a general purpose filter architecture.
The need in the art is addressed by the equalization system and method of the present invention. In a most general sense, the inventive equalization system includes first and second filters for filtering an in-phase component of a received signal in accordance with first and second sets of coefficients, respectively. The system includes third and fourth filters for filtering a quadrature component of the input signal in accordance with third and fourth sets of coefficients, respectively. The outputs of the first and third filters are subtracted to provide an equalized in-phase output signal and the outputs of the second and fourth filters are added to provide an equalized quadrature output signal.
In the illustrative embodiment the filters are finite impulse response filters and the coefficients are provided by a microprocessor. In accordance with the present teachings, the filters are implemented in a general purpose filter. The delay elements of the filters are calculated in accordance with a mean square error algorithm. Accordingly, the coefficients are the product of the correlation between inputs to the delay elements and a cross correlation between the inputs and a set of values representative of a desired response.
In an illustrative application, the system is implemented in a digital receiver having an antenna for receiving a radio frequency signal. A first signal processor is disposed in a first channel for processing the received signal and providing a first baseline signal in response thereto. A second signal processor disposed in a second channel for processing the received signal and providing a second baseline signal in response thereto. The receiver includes first and second analog to digital converters for processing the first and second baseline signals, respectively, and providing first digitized baseline signals in response thereto. A circuit is included for equalizing the first and second baseline signals. The equalizing circuit includes first and second equalizers disposed in the first and second channels respectively. Each of the equalizers comprises first and second filters for filtering an in-phase component of a received signal in accordance with first and second sets of coefficients, respectively. Third and fourth filters are included for filtering a quadrature component of the input signal in accordance with third and fourth sets of coefficients, respectively. A subtractor is included for subtracting the outputs of the first and third filters to provide an equalized in-phase output signal. The outputs of the second and fourth filters are added to provide an equalized quadrature output signal. The equalizing circuit further includes a processor for providing the coefficients. The outputs of the first and second equalizers are combined to provide the output of the receiver.